Exploiting the Potential of a Network of IRAMs

Recently, a great deal of research has gone into reducing the gap in performance between processors and their memory systems. Techniques such as prefetching have been developed in order to hide the long latencies involved in retrieving data from oo-chip DRAM. However, applications with irregular access patterns generally see greatly reduced beneet from these techniques, and latencies are becoming too large to hide eeectively even for well behaved applications. One solution to this problem is to move the DRAM onto the processor, reducing memory latencies by a large factor. However, only so much DRAM can be placed on a single chip. In order to overcome this limitation I propose using a multiprocessor system of IRAMs. In this paper I describe how such a system can be used eeectively to run uniprocessor applications.